This patent relates to a semiconductor device, and more particularly, to a method for fabricating a fine pattern of partially different critical dimensions (CDs) by lithography process.
Semiconductor devices may be integrated on a wafer by lithography using a photomask. To meet the growing needs for smaller and higher-performance semiconductor devices, developers work toward making technologies that can fabricate much finer patterns on a wafer. Wafer pattern size depends on, among other things, the limitation of exposure resolution of lithography. Therefore, a variety of technologies that can overcome the limitation of exposure resolution have been developed in order for fabrication of much finer patterns.
A double expose & etch technology (DEET) is proposed as a fabrication technology of sub-50 nm semiconductor devices. According to the DEET, spacers are formed and fine patterns are then formed using the spacers as an etch mask. The forming of the spacer includes forming a sacrificial pattern on an etch target layer, depositing spacer layer on sidewalls of the sacrificial pattern, and performing a spacer etch process. The sacrificial pattern is selectively removed, and fine patterns are formed by etching the underlying etch target layer using the spacers as an etch mask.
The shape of the fine pattern is determined by the shape of the spacer. Since the spacer is attached to the sidewalls of the sacrificial pattern, the spacer has a shape of a loop shape or rim shape line pattern attached to the sidewalls of the sacrificial pattern. Therefore, the fine pattern is also formed in a shape of the loop shape line pattern. In the actual fabrication process, however, a gate pattern, a bit line pattern, or an interconnection wire pattern, which will be formed on a semiconductor substrate, is not a loop type line pattern. Thus, an interconnection portion of the loop shape pattern needs to be selectively etched and separated. After a first exposure process and a first etch process of forming the sacrificial pattern, a second exposure process and a second etch process for separation are subsequently performed. Therefore, the formation of the fine pattern requires the exposure process and the etch process to be performed at least two times. Hence, at least two different photomasks are needed.
Since the fine pattern is formed by the etch process using the spacer as the etch mask, a CD of the fine pattern is determined depending on a CD of the spacer. Therefore, when forming fine patterns with different CDs at the same layer level, a third exposure process and a third etch process using an additional third photomask may be performed for forming the different size fine patterns.
In a semiconductor memory device, gate patterns of cell transistors are arranged with the substantially same CD at the same spacing. However, interconnection pads for transferring circuit signals to the gate patterns are provided to be positioned at edges of the respective gate patterns. When the gate patterns are formed by the fine pattern fabrication process using the spacer, a third exposure process and a third etch process using an additional third photomask may be performed for forming the interconnection pads, which have a larger CD and are connected to the gate patterns. Since the exposure process is performed three times, the number of required photomasks increases and thus the development expense for new device increases. In addition, an overlay margin between the exposure processes decreases and the complexity of an entire fabrication process increases. Furthermore, it may take a relatively longer time to perform the fabrication process and develop the semiconductor fabrication process.